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jfet input instrumentation amplifier with rail-to-rail output in msop package ad8220 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006C2010 analog devices, inc. all rights reserved. features low input currents 10 pa maximum input bias current (b grade) 0.6 pa maximum input offset current (b grade) high cmrr 100 db cmrr (minimum), g = 10 (b grade) 80 db cmrr (minimum) to 5 khz, g = 1 (b grade) excellent ac specifications and low power 1.5 mhz bandwidth (g = 1) 14 nv/hz input noise (1 khz) slew rate: 2 v/s 750 a quiescent supply current (maximum) versatile msop package rail-to-rail output input voltage range to below negative supply rail 4 kv esd protection 4.5 v to 36 v single supply 2.25 v to 18 v dual supply gain set with single resistor (g = 1 to 1000) qualified for automotive applications applications medical instrumentation precision data acquisition transducer interfaces pin configuration top view (not to scale) 03579-005 ?in 1 r g 2 r g 3 +in 4 +v s 8 v out 7 ref 6 ?v s 5 ad8220 figure 1. 10n 1n 100p 10p 1p 0.1p ?50 150 03579-059 temperature (c) input bias current (a) ?25 0 25 50 75 100 125 i os i bias figure 2. input bias current and offset current vs. temperature general description the ad8220 is the first single-supply, jfet input instrumentation amplifier available in an msop package. designed to meet the needs of high performance, portable instrumentation, the ad8220 has a minimum common-mode rejection ratio (cmrr) of 86 db at dc and a minimum cmrr of 80 db at 5 khz for g = 1. maxi- mum input bias current is 10 pa and typically remains below 300 pa over the entire industrial temperature range. despite the jfet inputs, the ad8220 typically has a noise corner of only 10 hz. with the proliferation of mixed-signal processing, the number of power supplies required in each system has grown. the ad8220 is designed to alleviate this problem. the ad8220 can operate on a 18 v dual supply, as well as on a single +5 v supply. its rail-to-rail output stage maximizes dynamic range on the low voltage supplies common in portable applications. its ability to run on a single 5 v supply eliminates the need to use higher voltage, dual supplies. the ad8220 draws a maximum of 750 a of quiescent current, making it ideal for battery powered devices. gain is set from 1 to 1000 with a single resistor. increasing the gain increases the common-mode rejection. measurements that need higher cmrr when reading small signals benefit when the ad8220 is set for large gains. a reference pin allows the user to offset the output voltage. this feature is useful when interfacing with analog-to-digital converters. the ad8220 is available in an msop that takes roughly half the board area of an soic. performance for the a and b grade is specified over the industrial temperature range of ?40c to +85c, and the w grade is specified over the automotive temperature range of ?40c to +125c.
ad8220 rev. b | page 2 of 28 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? pin configuration ............................................................................. 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? absolute maximum ratings ............................................................ 8 ? esd caution .................................................................................. 8 ? pin configuration and function descriptions ............................. 9 ? typical performance characteristics ........................................... 10 ? theory of operation ...................................................................... 19 ? gain selection ............................................................................. 20 ? layout ........................................................................................... 20 ? reference terminal .................................................................... 21 ? power supply regulation and bypassing ................................ 21 ? input bias current return path ............................................... 21 ? input protection ......................................................................... 21 ? rf interference ........................................................................... 22 ? common-mode input voltage range ..................................... 22 ? driving an adc ......................................................................... 22 ? applications information .............................................................. 23 ? ac-coupled instrumentation amplifier ................................ 23 ? differential output .................................................................... 23 ? electrocardiogram signal conditioning ................................. 25 ? outline dimensions ....................................................................... 26 ? ordering guide .......................................................................... 26 ? automotive products ................................................................. 26 ? revision history 5/10rev. a to rev. b added w grade .................................................................. universal changes to features section and general description section . 1 changes to specifications section and table 1 ............................. 3 changes to table 2 ............................................................................ 5 updated outline dimensions ....................................................... 26 changes to ordering guide .......................................................... 26 added automotive products section .......................................... 26 5/07rev. 0 to rev. a changes to table 1 ............................................................................. 3 changes to table 2 ............................................................................. 5 changes to table 3 ............................................................................. 8 changes to figure 6 and figure 7 ................................................. 10 changes to figure 23 and figure 24............................................. 13 changes to theory of operation .................................................. 19 changes to layout .......................................................................... 20 changes to ordering guide .......................................................... 26 4/06revision 0: initial version
ad8220 rev. b | page 3 of 28 specifications v s + = 15 v, v s ? = ?15 v, v ref = 0 v, t a = 25c, t opr = ?40c to +85c for a and b grades. t opr = ?40c to +125c for w grade, g = 1, r l = 2 k 1 , unless otherwise noted. table 1. a grade b grade w grade parameter test conditions min typ max min typ max min typ max unit common-mode rejection ratio (cmrr) t a for a, b grades, t opr for w grade cmrr dc to 60 hz with 1 k source imbalance v cm = 10 v g = 1 78 86 77 db g = 10 94 100 92 db g = 100 94 100 92 db g = 1000 94 100 92 db cmrr at 5 khz v cm = 10 v g = 1 74 80 72 db g = 10 84 90 80 db g = 100 84 90 80 db g = 1000 84 90 80 db noise rti noise = (e ni 2 + (e no /g) 2 ), t a voltage noise, 1 khz input voltage noise, e ni v in +, v in ? = 0 v 14 14 17 14 nv/hz output voltage noise, e no v in +, v in ? = 0 v 90 90 100 90 nv/hz rti, 0.1 hz to 10 hz g = 1 5 5 5 v p-p g = 1000 0.8 0.8 0.8 v p-p current noise f = 1 khz 1 1 1 fa/hz voltage offset v os = v osi + v oso /g input offset, v osi t a ?250 +250 ?125 +125 ?250 +250 v average tc t opr ?10 +10 ?5 +5 ?10 +10 v/c output offset, v oso t a ?750 +750 ?500 +500 ?750 +750 v average tc t opr ?10 +10 ?5 +5 ?10 +10 v/c offset rti vs. supply (psr) v s = 5 v to 15 v, t a for a, b grades, t opr for w grade g = 1 86 86 80 db g = 10 96 100 92 db g = 100 96 100 92 db g = 1000 96 100 92 db input current input bias current t a 25 10 25 pa over temperature t opr 0.3 0.3 100 na input offset current t a 2 0.6 2 pa over temperature t opr 0.005 0.005 10 na dynamic response small signal bandwidth, ?3 db t a g = 1 1500 1500 1500 khz g = 10 800 800 800 khz g = 100 120 120 120 khz g = 1000 14 14 14 khz
ad8220 rev. b | page 4 of 28 a grade b grade w grade parameter test conditions min typ max min typ max min typ max unit settling time 0.01% 10 v step, t a g = 1 5 5 5 s g = 10 4.3 4.3 4.3 s g = 100 8.1 8.1 8.1 s g = 1000 58 58 58 s settling time 0.001% 10 v step, t a g = 1 6 6 6 s g = 10 4.6 4.6 4.6 s g = 100 9.6 9.6 9.6 s g = 1000 74 74 74 s slew rate g = 1 to 100 t a 2 2 2 v/s gain g = 1 + (49.4 k/r g ), t a for a, b grades, t opr for w grade gain range 1 1000 1 1000 1 1000 v/v gain error v out = 10 v g = 1 ?0.06 +0.06 ?0.04 +0.04 ?0.1 +0.1 % g = 10 ?0.3 +0.3 ?0.2 +0.2 ?0.8 +0.8 % g = 100 ?0.3 +0.3 ?0.2 +0.2 ?0.8 +0.8 % g = 1000 ?0.3 +0.3 ?0.2 +0.2 ?0.8 +0.8 % gain nonlinearity v out = ?10 v to +10 v, t a g = 1 r l = 10 k 10 15 10 15 10 15 ppm g = 10 r l = 10 k 5 10 5 10 5 10 ppm g = 100 r l = 10 k 30 60 30 60 30 60 ppm g = 1000 r l = 10 k 400 500 400 500 400 500 ppm g = 1 r l = 2 k 10 15 10 15 10 15 ppm g = 10 r l = 2 k 10 15 10 15 10 15 ppm g = 100 r l = 2 k 50 75 50 75 50 75 ppm gain vs. temperature g = 1 3 10 2 5 3 10 ppm/c g > 10 ?50 ?50 ?50 ppm/c input impedance (pin to ground) 2 t a 10 4 ||5 10 4 ||5 10 4 ||5 g||pf input operating voltage range 3 v s = 2.25 v to 18 v for dual supplies ?v s ? 0.1 +v s ? 2 ?v s ? 0.1 +v s ? 2 ?v s ? 0.1 +v s ? 2 v over temperature t opr ?v s ? 0.1 +v s ? 2.1 ?v s ? 0.1 +v s ? 2.1 ?v s ? 0.1 +v s ? 2.2 v output output swing r l = 10 k, t a ?14.7 +14.7 ?14.7 +14.7 ?14.7 +14.7 v over temperature t opr ?14.6 +14.6 ?14.6 +14.6 ?14.3 +14.3 v short-circuit current t a 15 15 15 ma reference input t a k r in 40 40 40 a i in v in +, v in ? = 0 v 70 70 70 v voltage range ?v s +v s ?v s +v s +v s v/v gain to output t a 1 0.0001 1 0.0001 1 0.0001 v/v
ad8220 rev. b | page 5 of 28 a grade b grade w grade parameter test conditions min typ max min typ max min typ max unit power supply v operating range 2.25 4 18 2.25 4 18 2.25 4 18 a quiescent current t a 750 750 750 a over temperature t opr 850 850 1000 a temperature range for specified performance t opr ?40 +85 ?40 +85 ?40 +125 c 1 when the output sinks more than 4 ma, use a 47 pf capacitor in parallel with the load to prevent ringing. otherwise, use a lar ger load, such as 10 k. 2 differential and common-mode input impedance ca n be calculated from the pin impedance: z diff = 2(z pin ); z cm = z pin /2. 3 the ad8220 can operate up to a diode drop below the negative supply but the b ias current increases shar ply. the input voltage range reflects the maximum allowable voltage where the input bias current is within the specification. 4 at this supply voltage, ensure that the input common-mode vo ltage is within the input volt age range specification. v s + = 5 v, v s ? = 0 v, v ref = 2.5 v, t a = 25c, t opr = ?40c to +85c for a and b grades. t opr = ?40c to +125c for w grade, g = 1, r l = 2 k 1 , unless otherwise noted. table 2. a grade b grade w grade parameter test conditions min typ max min typ max min typ max unit common-mode rejection ratio (cmrr) t a for a, b grades, t opr for w grade cmrr dc to 60 hz with 1 k source imbalance v cm = 0 to 2.5 v g = 1 78 86 77 db g = 10 94 100 92 db g = 100 94 100 92 db g = 1000 94 100 92 db cmrr at 5 khz v cm = 0 to 2.5 v g = 1 74 80 72 db g = 10 84 90 80 db g = 100 84 90 80 db g = 1000 84 90 80 db noise rti noise = (e ni 2 + (e no /g) 2 ), t a voltage noise, 1 khz v s = 2.5 v input voltage noise, e ni v in +, v in ? = 0 v, v ref = 0 v 14 14 17 14 nv/hz output voltage noise, e no v in +, v in ? = 0 v, v ref = 0 v 90 90 100 90 nv/hz rti, 0.1 hz to 10 hz g = 1 5 5 5 v p-p g = 1000 0.8 0.8 0.8 v p-p current noise f = 1 khz 1 1 1 fa/hz voltage offset v os = v osi + v oso /g input offset, v osi t a ?300 +300 ?200 +200 ?300 +300 v average tc t opr ?10 +10 ?5 +5 ?10 10 v/c output offset, v oso t a ?800 +800 ?600 +600 ?800 +800 v average tc t opr ?10 +10 ?5 +5 ?10 +10 v/c offset rti vs. supply (psr) t a for a, b grades, t opr for w grade g = 1 86 86 80 db g = 10 96 100 92 db g = 100 96 100 92 db g = 1000 96 100 92 db
ad8220 rev. b | page 6 of 28 a grade b grade w grade parameter test conditions min typ max min typ max min typ max unit input current input bias current t a 25 10 25 pa over temperature t opr 0.3 0.3 100 na input offset current t a 2 0.6 2 pa over temperature t opr 0.005 0.005 10 na dynamic response t a small signal bandwidth, ?3 db g = 1 1500 1500 1500 khz g = 10 800 800 800 khz g = 100 120 120 120 khz g = 1000 14 14 14 khz settling time 0.01% t a g = 1 3 v step 2.5 2.5 2.5 s g = 10 4 v step 2.5 2.5 2.5 s g = 100 4 v step 7.5 7.5 7.5 s g = 1000 4 v step 30 30 30 s settling time 0.001% t a g = 1 3 v step 3.5 3.5 3.5 s g = 10 4 v step 3.5 3.5 3.5 s g = 100 4 v step 8.5 8.5 8.5 s g = 1000 4 v step 37 37 37 s slew rate g = 1 to 100 t a 2 2 2 v/s gain g = 1 + (49.4 k/r g ), t a for a, b grades, t opr for w grade gain range 1 1000 1 1000 1 1000 v/v gain error v out = 0.3 v to 2.9 v for g = 1, v out = 0.3 v to 3.8 v for g > 1 g = 1 ?0.06 +0.06 ?0.04 +0.04 ?0.1 +0.1 % g = 10 ?0.3 +0.3 ?0.2 +0.2 ?0.8 +0.8 % g = 100 ?0.3 +0.3 ?0.2 +0.2 ?0.8 +0.8 % g = 1000 ?0.3 +0.3 ?0.2 +0.2 ?0.8 +0.8 % nonlinearity v out = 0.3 v to 2.9 v for g = 1, v out = 0.3 v to 3.8 v for g > 1, t a g = 1 r l = 10 k 35 50 35 50 50 ppm g = 10 r l = 10 k 35 50 35 50 50 ppm g = 100 r l = 10 k 50 75 50 75 75 ppm g = 1000 r l = 10 k 650 750 650 750 750 ppm g = 1 r l = 2 k 35 50 35 50 50 ppm g = 10 r l = 2 k 35 50 35 50 50 ppm g = 100 r l = 2 k 50 75 50 75 75 ppm gain vs. temperature g = 1 3 10 2 5 3 10 ppm/c g > 10 ?50 ?50 ?50 ppm/c input impedance (pin to ground) 2 t a 10 4 ||6 10 4 ||6 10 4 ||6 g||pf input voltage range 3 t a ?0.1 +v s ? 2 ?0.1 +v s ? 2 v over temperature t opr ?0.1 +v s ? 2.1 ?0.1 +v s ? 2.1 ?0.1 +v s ? 2.2 v
ad8220 rev. b | page 7 of 28 a grade b grade w grade parameter test conditions min typ max min typ max min typ max unit output output swing r l = 10 k 0.15 4.85 0.15 4.85 0.15 4.85 v over temperature t opr 0.2 4.80 0.2 4.80 0.3 4.70 v short-circuit current 15 15 15 ma reference input t a r in 40 40 40 k i in v in +, v in ? = 0 v 70 70 70 a voltage range ?v s +v s ?v s +v s ?v s +v s v gain to output t a 1 0.0001 1 0.0001 1 0.0001 v/v power supply operating range 4.5 36 4.5 36 4.5 36 v quiescent current t a 750 750 750 a over temperature t opr 850 850 1000 a temperature range t opr , for specified performance t opr ?40 +85 ?40 +85 ?40 +125 c 1 when the output sinks more than 4 ma, use a 47 pf capacitor in parallel with the load to prevent ringing. otherwise, use a lar ger load, such as 10 k. 2 differential and common-mode impedance can be calculated from the pin impedance: z diff = 2(z pin ); z cm = z pin /2. 3 the ad8220 can operate up to a diode drop below the negative supply but the b ias current increases shar ply. the input voltage range reflects the maximum allowable voltage where the input bias current is within the specification.
ad8220 rev. b | page 8 of 28 absolute maximum ratings table 3. parameter rating supply voltage 18 v power dissipation see figure 3 output short-circuit current indefinite 1 input voltage (common mode) vs differential input voltage vs storage temperature range ?65c to +125c operating temperature range 2 ?40c to +125c lead temperature (soldering 10 sec) 300c junction temperature 140c ja (4-layer jedec standard board) 135c/w package glass transition temperature 140c esd (human body model) 4 kv esd (charge device model) 1 kv esd (machine model) 0.4 kv 1 assumes the load is referenced to midsupply. 2 temperature for specifie d performance is ?40c to +85c. for performance to 125c, see the typical perfor mance characteristics section. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. figure 3 shows the maximum safe power dissipation in the package vs. the ambient temperature for the msop on a 4-layer jedec standard board. ja values are approximations. 2.00 0 ?40 120 03579-045 ambient temperature (c) maximum power dissipation (w) 1.75 1.50 1.25 1.00 0.75 0.50 0.25 ?20 0 20 40 60 80 100 figure 3. maximum power dissipation vs. ambient temperature esd caution
ad8220 rev. b | page 9 of 28 pin configuration and fu nction descriptions top view (not to scale) 03579-005 ?in 1 r g 2 r g 3 +in 4 +v s 8 v out 7 ref 6 ?v s 5 ad8220 figure 4. pin configuration table 4. pin function descriptions pin o. neonic description 1 ?in negative input terminal (true differential input) 2, 3 r g gain setting terminals (place resistor across the r g pins) 4 +in positive input terminal (true differential input) 5 ?v s negative power supply terminal 6 ref reference voltage terminal (drive this terminal with a low impedance voltage source to level-shift the output) 7 v out output terminal 8 +v s positive power supply terminal
ad8220 rev. b | page 10 of 28 typical performance characteristics 0 03579-060 cmrr (v/v) number of units 1200 1000 800 600 400 200 ?40 ?20 0 20 40 figure 5. typical distribution of cmrr (g = 1) 0 03579-061 v osi (v) number of units 1000 800 600 400 200 ?200 ?100 0 100 200 figure 6. typical distributi on of input offset voltage 0 03579-062 v oso (v) number of units 1000 800 600 400 200 ?1000 ?500 0 500 1000 figure 7. typical distribution of output offset voltage 0 03579-063 i bias (pa) number of units 1600 1400 1200 1000 800 600 400 200 0 1 2 3 4 5 figure 8. typical distributi on of input bias current 0 03579-064 i os (pa) number of units 1200 1000 800 600 400 200 ?0.2 ?0.1 0 0.1 0.2 figure 9. typical distribution of input offset current 1000 1 1100k 03579-042 frequency (hz) voltage noise rti (nv/ hz) 10 100 1k 10k 10 100 gain = 100 bandwidth roll-off gain = 1 gain = 10 gain = 100/gain = 1000 gain = 1000 bandwidth roll-off figure 10. voltage spectral density vs. frequency
ad8220 rev. b | page 11 of 28 xx xx xx xx 03579-024 xxx (x) xxx (x) 1s/div 5v/div figure 11. 0.1 hz to 10 hz rti voltage noise (g = 1) xx xx xx xx 03579-025 xxx (x) xxx (x) 1s/div 1v/div figure 12. 0.1 hz to 10 hz rti voltage noise (g = 1000) 8 0 0.1 1k 03579-009 time (s) v osi (v) 1 10 100 7 6 5 4 3 2 1 figure 13. change in input offset voltage vs. warmup time 150 10 11m 03579-035 frequency (hz) psrr (db) 10 100 1k 10k 100k 130 110 90 70 50 30 bandwidth limited gain = 1 gain = 10 gain = 100 gain = 1000 figure 14. positive psrr vs. frequency, rti 150 10 11m 03579-040 frequency (hz) psrr (db) 10 100 1k 10k 100k 130 110 90 70 50 30 gain = 1 gain = 10 gain = 100 gain = 1000 figure 15. negative psrr vs. frequency, rti ?1 1 3 5 7 9 ?16 16 03579-050 common-mode voltage (v) input bias current (pa) input offset current (pa) ?12 ?8 ?4 0 4 8 12 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 input offset current 5 ?15.1v ?5.1v input offset current 15 input bias current 15 input bias current 5 figure 16. input bias current and input offset current vs. common-mode voltage
ad8220 rev. b | page 12 of 28 10n 1n 100p 10p 1p 0.1p ?50 150 03579-059 temperature (c) input bias current (a) ?25 0 25 50 75 100 125 i os i bias figure 17. input bias current and offset current vs. temperature, v s = 15 v, v ref = 0 v 10n 1n 100p 10p 1p 0.1p ?50 150 03579-065 temperature (c) current (a) ?25 0 25 50 75 100 125 i os i bias figure 18. input bias current and offset current vs. temperature, v s = +5 v, v ref = 2.5 v 160 40 10 100k 03579-023 frequency (hz) cmrr (db) 100 1k 10k 140 120 100 80 60 gain = 1 gain = 10 gain = 100 gain = 1000 bandwidth limited figure 19. cmrr vs. frequency 160 40 1 100k 03579-051 frequency (hz) cmrr (db) 140 120 100 80 60 gain = 1 gain = 10 gain = 1000 bandwidth limited gain = 100 10 100 1k 10k figure 20. cmrr vs. frequency, 1 k source imbalance 10 ?10 ?50 130 03579-034 temperature (c) cmrr ( v/v) 8 6 4 2 0 ?2 ?4 ?6 ?8 ?30 ?10 10 30 50 70 90 110 figure 21. change in cmrr vs. temperature, g = 1 70 ?40 100 10m 03579-022 frequency (hz) gain (db) 1k 10k 100k 1m 60 50 40 30 20 10 0 ?10 ?20 ?30 gain = 1 gain = 10 gain = 100 gain = 1000 figure 22. gain vs. frequency
ad8220 rev. b | page 13 of 28 03579-026 output voltage (v) xxx nonlinearity (5ppm/div) ?8?10 ?6 ?4 ?2 0 2 4 6 8 10 r load = 2k ? r load = 10k ? v s = 15v figure 23. gain nonlinearity, g = 1 03579-027 output voltage (v) xxx nonlinearity (5ppm/div) ?8?10 ?6 ?4 ?2 0 2 4 6 8 10 r load = 2k ? r load = 10k ? v s = 15v figure 24. gain nonlinearity, g = 10 03579-028 output voltage (v) xxx nonlinearity (50ppm/div) ?8 ?10 ?6?4?20246810 r load =2k ? r load = 10k ? v s = 15v figure 25. gain nonlinearity, g = 100 03579-029 output voltage (v) xxx nonlinearity (500ppm/div) ?8 ?10 ?6?4?20246810 r load =2k ? r load =10k ? v s = 15v figure 26. gain nonlinearity, g = 1000 18 ?18 ?16 16 03579-037 output voltage (v) input common-mode voltage (v) 12 6 0 ?6 ?12 ?12 ?8 ?4 0 4 8 12 ?15.3v +13v 15v supplies 5v supplies +14.9v, ?8.3v +14.9v, +5.5v +4.95v, ?3.3v +4.95v, +0.6v ?14.8v, +5.5v ?14.8v, ?8.3v ?4.8v, ?3.3v ?4.8v, +0.6v ?5.3v +3v figure 27. input common-mode voltage range vs. output voltage, g = 1, v ref = 0 v 012345 4 ?1 ?1 6 03579-036 output voltage (v) input common-mode voltage (v) 3 2 1 0 ?0.3v +3v +4.9v, +0.5v +4.9v, +1.7v +5vsinglesupply, v ref = +2.5v +0.1v, +0.5v +0.1v, +1.7v figure 28. input common-mode voltage range vs. output voltage, g = 1, v s = +5 v, v ref = 2.5 v
ad8220 rev. b | page 14 of 28 18 ?18 ?16 16 03579-039 output voltage (v) input common-mode voltage (v) 12 6 0 ?6 ?12 ?12 ?8 ?4 0 4 8 12 +13v ?15.3v 15v supplies +14.9v, ?9v +14.9v, +5.4v +4.9v, +0.5v +4.9v, ?4.1v ?4.9v, +0.4v ?4.9v, ?4.1v ?5.3v +3v ?14.8v, ?9v ?14.9v, +5.4v 5v supplies figure 29. input common-mode voltage range vs. output voltage, g = 100, v ref = 0 v 012345 4 ?1 ?1 6 03579-038 output voltage (v) input common-mode voltage (v) 3 2 1 0 +3v ?0.3v +4.9v, +1.7v +4.9v, ?0.5v +0.1v, +1.7v +0.1v, ?0.5v +5v single supply, v ref = +2.5v figure 30. input common-mode voltage range vs. output voltage, g = 100, v s = +5 v, v ref = 2.5 v v s + ?1 218 03579-052 supply voltage (v) input voltage limit (v) ?1 ?2 +1 v s ? 4 6 8 10121416 ?40c +125c +25c +85c +25c ?40c notes 1. the ad8220 can operate up to a v be below the negative supply, but the bias current will increase sharply. +85c +125c figure 31. input voltage limit vs. supply voltage, g = 1, v ref =0 v v s + v s ? 218 03579-053 dual supply voltage (v) output voltage swing (v) referred to supply voltage ?1 ?2 ?3 ?4 +4 +3 +2 +1 4 6 8 10 12 14 16 ?40c +25c +125c +85c ?40c +25c +85c +125c figure 32. output voltage swing vs. supply voltage, r load = 2 k, g = 10, v ref = 0 v v s + v s ? 218 03579-054 dual supply voltage (v) output voltage swing (v) referred to supply voltage ?0.2 ?0.4 +0.4 +0.2 4 6 8 10 12 14 16 +85c +125c +25c ?40c ?40c +25c +85c +125c figure 33. output voltage swing vs. supply voltage, r load = 10 k, g = 10, v ref = 0 v 15 ?15 100 10k 03579-055 r load ( ? ) output voltage swing (v) 1k 10 5 0 ?5 ?10 +125c +85c +25c ?40c +125c +85c +25c ?40c figure 34. output voltage swing vs. load resistance v s = 15 v, v ref = 0 v
ad8220 rev. b | page 15 of 28 5 0 100 10k 03579-056 r load ( ? ) output voltage swing (v) 1k 4 3 2 1 ?40c ?40c +125c +125c +25c +25c +85c +85c figure 35. output voltage swing vs. load resistance v s = +5 v, v ref = 2.5 v v s + v s ? 016 03579-057 i out (ma) output voltage swing (v) referred to supply voltages ?1 ?2 ?3 ?4 +4 +3 +2 +1 2468101214 ?40c +125c +85c +25c ?40c +25c +85c +125c figure 36. output voltage swing vs. output current, v s = 15 v, v ref = 0 v v s + v s ? 016 03579-058 i out (ma) output voltage swing (v) referred to supply voltages ?1 ?2 +2 +1 2468101214 ?40c +125c +85c +25c +125c +25c +85c figure 37. output voltage swing vs. output current, v s = 5 v, v ref = 2.5 v x x xx xx xx 03579-018 xxx (x) xxx (x) 5s/div 20mv/div 100pf 47pf no load figure 38. small signal pulse response for various capacitive loads, v s = 15 v, v ref = 0 v x x xx xx xx 03579-019 xxx (x) xxx (x) 5s/div 20mv/div 100pf 47pf no load figure 39. small signal pulse response for various capacitive loads, v s = 5 v, v ref = 2.5 v 35 0 100 10m 03579-021 frequency (hz) output voltage swing (v p-p) 1k 10k 100k 1m 30 25 20 15 10 5 gain = 1 gain = 10, 100, 1000 figure 40. output voltage swing vs . large signal frequency response
ad8220 rev. b | page 16 of 28 xx xx xx xx 03579-046 xxx (x) xxx (x) 20s/div 5s to 0.01% 6s to 0.001% 5v/div 0.002%/div figure 41. large signal pulse response and settle time, g = 1, r load = 10 k, v s = 15 v, v ref = 0 v xx xx xx xx 03579-047 xxx (x) xxx (x) 20s/div 5v/div 4.3 sto0.01% 4.6 sto0.001% 0.002%/div figure 42. large signal pulse response and settle time, g = 10, r load = 10 k, v s = 15 v, v ref = 0 v xx xx xx xx 03579-048 xxx (x) xxx (x) 20s/div 8.1 s to 0.01% 9.6 s to 0.001% 0.002%/div 5v/div figure 43. large signal pulse response and settle time, g = 100, r load = 10 k, v s = 15 v, v ref = 0 v x x xx xx xx 03579-049 xxx (x) xxx (x) 200s/div 58 sto0.01% 74 sto0.001% 0.002%/div 5v/div figure 44. large signal pulse response and settle time, g = 1000, r load = 10 k, v s = 15 v, v ref = 0 v 03579-016 xxx xxx 4s/div 20mv/div figure 45. small signal pulse response, g = 1, r load = 2 k, c load = 100 pf, v s = 15 v, v ref = 0 v 03579-014 xxx xxx 4s/div 20mv/div figure 46. small signal pulse response, g = 10, r load = 2 k, c load = 100 pf, v s = 15 v, v ref = 0 v
ad8220 rev. b | page 17 of 28 03579-012 xxx xxx 4s/div 20mv/div figure 47 small signal pulse response, g = 100, r load = 2 k, c load = 100 pf, v s = 15 v, v ref =0 v 03579-010 xxx xxx 20mv/div 40s/div figure 48. small signal pulse response, g = 1000, r load = 2 k, c load = 100 pf, v s = 15 v, v ref = 0 v 03579-017 xxx xxx 4s/div 20mv/div figure 49. small signal pulse response, g = 1, r load = 2 k, c load = 100 pf, v s = 5 v, v ref = 2.5 v 03579-015 xxx xxx 4s/div 20mv/div figure 50. small signal pulse response, g = 10, r load = 2 k, c load = 100 pf, v s = 5 v, v ref = 2.5 v 03579-013 xxx xxx 4s/div 20mv/div figure 51. small signal pulse response, g = 100, r load = 2 k, c load = 100 pf, v s = 5 v, v ref = 2.5 v 03579-011 xxx xxx 40s/div 20mv/div figure 52. small signal pulse response, g = 1000, r load = 2 k, c load = 100 pf, v s = 5 v, v ref = 2.5 v
ad8220 rev. b | page 18 of 28 15 0 020 03579-043 output voltage step size (v) settling time (s) 10 5 51 01 5 settled to 0.01% settled to 0.001% figure 53. settling time vs. output vo ltage step size (g = 1) 15 v, v ref = 0 v 100 1 1 1000 03579-041 gain (v/v) settling time (s) 10 100 10 settled to 0.01% settled to 0.001% figure 54. settling time vs. gain for a 10 v step, v s = 15 v, v ref = 0 v
ad8220 rev. b | page 19 of 28 theory of operation q2 q1 node a node b node c node d vb c1 c2 a1 a2 ?v s +v s ?v s j1 + in v pinch +v s ?v s j2 ?in v pinch + v s ?v s r g + v s + v s + v s ?v s 20k ? 20k ? 20k ? 20k ? +v s ?v s +v s ?v s ref output a3 node e node f i i r2 24.7k ? r1 24.7k ? 03579-006 figure 55. simplified schematic the ad8220 is a jfet input, monolithic instrumentation amplifier based on the classic 3-op amp topology (see figure 55). input transistor j1 and input transistor j2 are biased at a fixed current so that any input signal forces the output voltages of a1 and a2 to change accordingly; the input si gnal creates a current through r g that flows in r1 and r2 such that the outputs of a1 and a2 provide the correct, gained signal. topologically, j1, a1, and r1 and j2, a2, and r2 can be viewed as precision current feedback amplifiers that have a gain bandwidth of 1.5 mhz. the common-mode voltage and amplified differential signal from a1 and a2 are applied to a difference amplifier that rejects the common-mode voltage but amplifies the differential signal. the difference amplifier employs 20 k laser-trimmed resistors that result in an in-amp with gain error less than 0.04%. new trim techniques were developed to ensure that cmrr exceeds 86 db (g = 1). using jfet transistors, the ad8220 offers an extremely high input impedance, extremely low bias currents of 10 pa maximum, a low offset current of 0.6 pa maximum, and no input bias current noise. in addition, input offset is less than 125 v and drift is less than 5 v/c. ease of use and robustness were considered. a common problem for instrumentation amplifiers is that at high gains, when the input is overdriven, 1 an excessive milliampere input bias current can result and the output can undergo phase reversal. the ad8220 has none of these problems; its input bias current is limited to less than 10 a, and the output does not phase reverse under overdrive fault conditions. 1 overdriving the input at high gains refers to when the input signal is within the supply voltages but the amplifier cannot output the gained signal. for example, at a gain of 100, driving the amplifier with 10 v on 15 v constitutes overdriving the inputs since the amplifier cannot output 100 v. the ad8220 has extremely low load-induced nonlinearity. all amplifiers that comprise the ad8220 have rail-to-rail output capability for enhanced dynamic range. the input of the ad8220 can amplify signals with wide common-mode voltages even slightly lower than the negative supply rail. the ad8220 operates over a wide supply voltage range. it can operate from either a single +4.5 v to +36 v supply or a dual 2.25 v to 18 v. the transfer function of the ad8220 is g r g k 49.4 1 ?? users can easily and accurately set the gain using a single, standard resistor. because the input amplifiers employ a current feedback architecture, the ad8220 gain-bandwidth product increases with gain, resulting in a system that does not suffer as much bandwidth loss as voltage feedback architectures at higher gains. a unique pinout enables the ad8220 to meet a cmrr specification of 80 db through 5 khz (g = 1). the balanced pinout, shown in figure 56, reduces parasitics that adversely affect cmrr performance. in addition, the new pinout simplifies board layout because associated traces are grouped together. for example, the gain setting resistor pins are adjacent to the inputs, and the reference pin is next to the output. top view (not to scale) 03579-005 ?in 1 r g 2 r g 3 +in 4 +v s 8 v out 7 ref 6 ?v s 5 ad8220 figure 56. pin configuration
ad8220 rev. b | page 20 of 28 gain selection placing a resistor across the r g terminals sets the ad8220 gain, which can be calculated by referring to table 5 or by using the gain equation 1 k 4.49 ? ? g r g table 5. gains achieved using 1% resistors 1% standard table value of rg () calculated gain 49.9 k 1.990 12.4 k 4.984 5.49 k 9.998 2.61 k 19.93 1.00 k 50.40 499 100.0 249 199.4 100 495.0 49.9 991.0 the ad8220 defaults to g = 1 when no gain resistor is used. gain accuracy is determined by the absolute tolerance of r g . the tc of the external gain resistor increases the gain drift of the instrumentation amplifier. gain error and gain drift are kept to a minimum when the gain resistor is not used. layout careful board layout maximizes system performance. in applications that need to take advantage of the low input bias current of the ad8220, avoid placing metal under the input path to minimize leakage current. to maintain high cmrr over frequency, lay out the input traces symmetrically and lay out the traces of the r g resistor symmetrically. ensure that the traces maintain resistive and capacitive balance; this holds for additional pcb metal layers under the input and r g pins. traces from the gain setting resistor to the r g pins should be kept as short as possible to minimize parasitic inductance. an example layout is shown in figure 57 and figure 58. to ensure the most accurate output, the trace from the ref pin should either be connected to the ad8220 local ground (see figure 59) or connected to a voltage that is referenced to the ad8220 local ground. common-mode rejection ratio (cmrr) the ad8220 has high cmrr over frequency giving it greater immunity to disturbances, such as line noise and its associated harmonics, in contrast to typical in-amps whose cmrr falls off around 200 hz. these in-amps often need common-mode filters at the inputs to compensate for this shortcoming. the ad8220 is able to reject cmrr over a greater frequency range, reducing the need for input common-mode filtering. a well-implemented layout helps to maintain the high cmrr over frequency of the ad8220. input source impedance and capacitance should be closely matched. in addition, source resistance and capacitance should be placed as close to the inputs as possible. grounding the output voltage of the ad8220 is developed with respect to the potential on the reference terminal. care should be taken to tie ref to the appropriate local ground (see figure 59). in mixed-signal environments, low level analog signals need to be isolated from the noisy digital environment. many adcs have separate analog and digital ground pins. although it is convenient to tie both grounds to a single ground plane, the current traveling through the ground wires and pc board can cause a large error. therefore, separate analog and digital ground returns should be used to minimize the current flow from sensitive points to the system ground. 03579-101 figure 57. example layout?top layer of the ad8220 evaluation board 03579-102 figure 58. example layout?bottom layer of the ad8220 evaluation board
ad8220 rev. b | page 21 of 28 reference terminal the reference terminal, ref, is at one end of a 20 k resistor (see figure 55). the output of the instrumentation amplifier is referenced to the voltage on the ref terminal; this is useful when the output signal needs to be offset to voltages other than common. for example, a voltage source can be tied to the ref pin to level-shift the output so that the ad8220 can interface with an adc. the allowable reference voltage range is a function of the gain, common-mode input, and supply voltages. the ref pin should not exceed either +v s or ?v s by more than 0.5 v. for best performance, especially in cases where the output is not measured with respect to the ref terminal, source impedance to the ref terminal should be kept low, because parasitic resistance can adversely affect cmrr and gain accuracy. power supply regulation and bypassing the ad8220 has high psrr. however, for optimal performance, a stable dc voltage should be used to power the instrumentation amplifier. noise on the supply pins can adversely affect performance. as in all linear circuits, bypass capacitors must be used to decouple the amplifier. a 0.1 f capacitor should be placed close to each supply pin. a 10 f tantalum capacitor can be used further away from the part (see figure 59). in most cases, it can be shared by other precision integrated circuits. ad8220 +v s +in ?in load ref 0.1f 10f 0.1f 10f ?v s v out 0 3579-001 figure 59. supply decoupling, ref and output referred to ground input bias current return path the ad8220 input bias current is extremely small at less than 10 pa. nonetheless, the input bias current must have a return path to common. when the source, such as a transformer, cannot provide a return current path, one should be created (see figure 60). +v s ref transformer ?v s ad8220 ac-coupled +v s ref c r r c ?v s ad8220 1 f high-pass = 2 rc 03579-002 figure 60. creating an i bias path input protection all terminals of the ad8220 are protected against esd. (esd protection is guaranteed to 4 kv, human body model.) in addition, the input structure allows for dc overload conditions a diode drop above the positive supply and a diode drop below the negative supply. voltages beyond a diode drop of the supplies cause the esd diodes to conduct and enable current to flow through the diode. therefore, an external resistor should be used in series with each of the inputs to limit current for voltages above +vs. in either scenario, the ad8220 safely handles a continuous 6 ma current at room temperature. for applications where the ad8220 encounters extreme overload voltages, as in cardiac defibrillators, external series resistors and low leakage diode clamps, such as bav199ls, fjh1100s, or sp720s, should be used.
ad8220 rev. b | page 22 of 28 rf interference rf rectification is often a problem in applications where there are large rf signals. the problem appears as a small dc offset voltage. the ad8220 by its nature has a 5 pf gate capacitance, c g , at its inputs. matched series resistors form a natural low-pass filter that reduces rectification at high frequency (see figure 61). the relationship between external, matched series resistors and the internal gate capacitance is expressed as follows: g diff rc filterfreq 2 1 ? g cm rc filterfreq 2 1 ? ad8220 v out c g c g ?v s ref ?v s r r +in ?in +15 v ?15v 0.1f 10f 0.1f 10f 03579-030 figure 61. rfi filtering without external capacitors to eliminate high frequency common-mode signals while using smaller source resistors, a low-pass rc network can be placed at the input of the instrumentation amplifier (see figure 62). the filter limits the input signal bandwidth according to the following relationship: ) 2(2 1 g cd diff cccr filterfreq ? ? ? )(2 1 g c cm ccr filterfreq ? ? mismatched c c capacitors result in mismatched low-pass filters. the imbalance causes the ad8220 to treat what would have been a common-mode signal as a differential signal. to reduce the effect of mismatched external c c capacitors, select a value of c d greater than 10 times c c . this sets the differential filter frequency lower than the common-mode frequency. r r ad8220 +15 v +in ?in 0.1f 10f 10f 0.1f ref v out ?15v c d c c c c 10nf 1nf 1nf 4.02k ? 4.02k ? 03579-003 figure 62. rfi suppression common-mode input voltage range the common-mode input voltage range is a function of the input range and the outputs of internal amplifier a1, internal amplifier a2, and internal amplifier a3, the reference voltage, and the gain. figure 27 to figure 30 show common-mode voltage ranges for various supply voltages and gains. driving an adc an instrumentation amplifier is often used in front of an adc to provide cmrr and additional conditioning, such as a voltage level shift and gain (see figure 63). in this example, a 2.7 nf capacitor and a 1 k resistor create an antialiasing filter for the ad7685 . the 2.7 nf capacitor also serves to store and deliver the necessary charge to the switched capacitor input of the adc. the 1 k series resistor reduces the burden of the 2.7 nf load from the amplifier. however, large source impedance in front of the adc can degrade thd. the example shown in figure 63 is for sub-60 khz applications. for higher bandwidth applications where thd is important, the series resistor needs to be small. at worst, a small series resistor can load the ad8220, potentially causing the output to overshoot or ring. in such cases, a buffer amplifier, such as the ad8615 , should be used after the ad8220 to drive the adc. ad8220 ad7685 4.7f adr435 +5v 2.7nf ref 1k ? 1.07k ? +2.5v +in ?in 50mv +5 v 0.1f 10f 0 3579-033 figure 63. driving an adc in a low frequency application
ad8220 rev. b | page 23 of 28 applications information ac-coupled instrumentation amplifier measuring small signals that are in the noise or offset of the amplifier can be a challenge. figure 64 shows a circuit that can improve the resolution of small ac signals. the large gain reduces the referred input noise of the amplifier to 14 nv/hz. therefore, smaller signals can be measured because the noise floor is lower. dc offsets that would have been gained by 100 are eliminated from the ad8220 output by the integrator feedback network. at low frequencies, the op1177 forces the ad8220 output to 0 v. once a signal exceeds f high-pass , the ad8220 outputs the amplified input signal. ad8220 op1177 r 15.8k ? + v s +in ?in 0.1f 0.1f 0.1f 0.1f 10f 10f ref c 1f ?v s ?v s +v s +v s ?v s r 499? 1 2 rc f high-pass = v ref 03579-004 figure 64. ac-coupled circuit differential output in certain applications, it is necessary to create a differential signal. new high resolution adcs often require a differential input. in other cases, transmission over a long distance can require differential processing for better immunity to interference. figure 65 shows how to configure the ad8220 to output a differential signal. an op1177 op amp is used to create a differential voltage. errors from the op amp are common to both outputs and are thus common mode. likewise, errors from using mismatched resistors cause a common-mode dc offset error. such errors are rejected in differential signal processing by differential input adcs or instrumentation amplifiers. when using this circuit to drive a differential adc, v ref can be set using a resistor divider from the reference of the adc to make the output ratiometric with the adc as shown in figure 66.
ad8220 rev. b | page 24 of 28 5v 0.1f +5v ?5v 4.99k ? 4.99k ? ad8220 op1177 +15 v +in ?in 0.1f 0.1f 10f ref +5v +15v ?15v v ref 2.5v v out a=+v in +v ref 2 v out b=?v in +v ref 2 0.1f ?15v +2.5v +5.0v +0v time amplitude +2.5v +5.0v +0v time amplitude time amplitude 03579-008 figure 65. differential output with level shift 5v 0.1f 4.99k ? 4.99k ? 4.99k ? 4.99k ? ad8220 op1177 +15 v +in ?in 0.1f 0.1f 10f ref +5v +15v ?15v v ref 2.5v v out a=+v in +v ref 2 0.1f ?15v time to 0v to +5v adc to 0v to +5v adc +ain ?ain ref +5v from reference +5v from reference 10nf v out b=?v in +v ref 2 0 3579-031 figure 66. configuring the ad8220 to ou tput a ratiometric, differential signal
ad8220 rev. b | page 25 of 28 electrocardiogram signal conditioning the ad8220 makes an excellent input amplifier for next generation ecgs. its small size, high cmrr over frequency, rail-to-rail output, and jfet inputs are well suited for this application. potentials measured on the skin range from 0.2 mv to 2 mv. the ad8220 solves many of the typical challenges of measuring these body surface potentials. the high cmrr of the ad8220 helps reject common-m ode signals that come in the form of line noise or high frequency emi from equipment in the operating room. its rail-to-rail output offers a wide dynamic range allowing for higher gains than would be possible using other instrumentation amplifiers. jfet inputs offer a large input capacitance of 5 pf. a natural rc filter is formed reducing high frequency noise when series input resistors are used in front of the ad8220 (see the rf interference section). in addition, the ad8220 jfet inputs have ultralow input bias current and no current noise, making it useful for ecg applications where there are often large impedances. the msop and the optimal pinout of the ad8220 allow smaller footprints and more efficient layout, paving the way for next-generation portable ecgs. figure 67 shows an example ecg schematic. following the ad8220 is a 0.033 hz high-pass filter, formed by the 4.7 f capacitor and the 1 m resistor, which removes the dc offset that develops between the electrodes. an additional gain of 50, provided by the ad8618 , makes use of the 0 v to 5 v input range of the adc. an active, fifth-order, low-pass bessel filter removes signals greater than approximately 160 hz. an op2177 buffers, inverts, and gains the common-mode voltage taken at the midpoint of the ad8220 gain setting resistors. this right- leg drive circuit helps cancel common-mode signals by inverting the common-mode signal and driving it back into the body. a 499 k series resistor at the output of the op2177 limits the current driven into the body. adc ad7685 ad8618 +5v 2.7nf 500 ? ad8618 14.5k ? 19.3k ? 2.5v 22nf 4.7f ref +5v reference adr435 68nf +5v ad8618 +5v 1.15k ? 4.99k ? 2.5v 2.5v 2.5v 33nf 19.3k ? 14.5k ? 33nf low-p a ss fifth order filter at 157hz ad8618 +5v ?5v ?5v +5v 47nf 14k ? 14k? 57.6k ? 1.18k ? g=+50 4.7f 2.5v 1m ? 12.7k ? 499k ? 220pf high-pass filter 0.033hz instrumentation amplifier g=+14 ad8220 +5v 4.12k ? 24.9k ? 24.9k ? ?5v +5v op amps op2177 op2177 866k ? 68pf ab c 03579-032 15k? ?5v +5v ?5v +5v 2.2pf 2.2pf 10pf 10k? 10k? figure 67. example ecg schematic
ad8220 rev. b | page 26 of 28 outline dimensions compliant to jedec standards mo-187-aa 100709-b 6 0 0.80 0.55 0.40 4 8 1 5 0.65 bsc 0.40 0.25 1.10 max 3.20 3.00 2.80 coplanarity 0.10 0.23 0.09 3.20 3.00 2.80 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 figure 68. 8-lead mini small outline package [msop] (rm-8) dimensions shown in millimeters ordering guide model 1 , 2 temperature range 3 package description package option branding ad8220armz ?40c to +85c 8-lead msop rm-8 h01 ad8220armz-rl ?40c to +85c 8-lead msop, 13" tape and reel rm-8 h01 ad8220armz-r7 ?40c to +85c 8-lead msop, 7" tape and reel rm-8 h01 ad8220brmz ?40c to +85c 8-lead msop rm-8 h0p ad8220brmz-rl ?40c to +85c 8-lead msop, 13" tape and reel rm-8 h0p ad8220brmz-r7 ?40c to +85c 8-lead msop, 7" tape and reel rm-8 h0p AD8220WARMZ ?40c to +125c 8-lead msop rm-8 y2d AD8220WARMZ-rl ?40c to +125c 8-lead msop, 13" tape and reel rm-8 y2d AD8220WARMZ-r7 ?40c to +125c 8-lead msop, 7" tape and reel rm-8 y2d 1 z = rohs compliant part. 2 w = qualified for auto motive applications. 3 see the typical performance characteristics sect ion for expected operat ion from 85c to 125c. automotive products the ad8220w models are available with controlled manufacturing to support the quality and reliability requirements of automotiv e applications. note that these automotive models may have specifications that differ from the commercial models; therefore, desi gners should review the specifications section of this data sheet carefully. only the automotive grade products shown are available f or use in automotive applications. contact your local analog devices account representative for specific product ordering information an d to obtain the specific automotive reliability reports for these models.
ad8220 rev. b | page 27 of 28 notes
ad8220 rev. b | page 28 of 28 notes ?2006C2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d03579-0-5/10(b)

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